The present invention relates generally to semiconductor device processing and more particularly to methods for fabricating flash memory cells in a semiconductor device.
Flash and other types of electronic memory devices are constructed of memory cells operative to individually store and provide access to binary information or data. The memory cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry using wordlines and bitlines. Conventional flash memories are constructed in a cell structure wherein one or more bits of information or data are stored in each flash memory cell. In typical single bit memory architectures, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well.
The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer. Such single bit memory architectures can be partitioned into multiple bits by programming partially. However, such electrical partition methods reduce the performance of the devices in terms of program, erase, and access speeds, as well as reliability.
Other types of memory devices include ones comprising silicon or polysilicon above and below the ONO layer, which are sometimes referred to as SONOS memory devices. Such devices may include physical dual bit memory cells, individually adapted to store two binary bits of data by localized charge trapping. The SONOS memory devices provide data retention with thin bottom oxide, low-voltage operation, and fast programming speed.
Dual bit memory cells are generally symmetrical, including two identical and interchangeable source/drain regions. Application of appropriate voltages to the gate, drain, and source terminals allows access to one of the two bits (e.g., for read, program, erase, verify, or other operations). Core cells in flash memory devices, whether single bit or multiple-bit, may be interconnected in a variety of different configurations. For instance, cells may be configured in a virtual ground type configuration, with the control gates of the cells in a row individually connected to a wordline. In addition, the source/drain regions of memory cells in a particular column are connected together by a conductive bitline. In operation, individual flash cells and the individual data bits thereof, are addressed via the respective bitlines connected to first and second source/drain regions thereof and a wordline connected to the gate using peripheral decoder and control circuitry for programming (writing), reading, erasing, or other functions.
As device densities increase and product dimensions decrease, it is desirable to reduce the size of individual memory cells, sometimes referred to as scaling. However, the fabrication techniques used to produce conventional dual-bit SONOS flash memory cells limit or inhibit the designer""s ability to reduce cell dimensions. In the preferred manufacturing processes, an ONO layer is formed on a substrate, over which a patterned resist is formed. An initial implantation is performed using the resist as a mask for selective introduction of dopant impurities into portions of the substrate next to prospective source/drain regions thereof. The initial implant typically provides a relatively low dosage of dopants at a relatively high energy. The resist is then removed and a thermal process is used to drive the dopants deeper into the substrate.
Thereafter, a second patterned resist mask is formed to expose the source/drain regions, followed by a second implantation at higher dosage and lower energy. After the implantations, the second resist is removed, and gate structures are formed over prospective channel regions of the cells, for example, using polysilicon. In order to scale the memory cell devices to facilitate increased device densities, it is desirable to narrow the length of the cell channel regions, and hence the length of the gate structures. However, process limitations in alignment of the first and second resist masks effectively limit the ability to scale the channel lengths of the memory cells while controlling the operating parameters of the device within desired performance specifications. Angled implants, such as halo or pocket implants, can be done with the source/drain implants in one mask, but this results in undesirably sharp dopant junctions because there is no thermal diffusion allowed between the two implants. Thus, there is a need for improved manufacturing techniques by which dual bit SONOS flash memory devices may be scaled without sacrificing device performance.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, the primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The invention provides methods for fabricating dual bit SONOS and other flash memory cells, involving formation of polysilicon gate structures over an ONO layer, and doping of source/drain regions of the substrate using the gate structures as an implant mask. The invention also provides memory fabrication methods in which dielectric material is formed over and between the gate structures, and the wafer is planarized using an STI-like planarization process, such as chemical mechanical polishing. The invention thus facilitates the manufacture of scaled memory devices using existing processing steps, such as STI CMP operations, which may be performed at multiple points in an overall process flow, thereby reducing the complexity of process development and optimization. In addition, the invention provides for self-alignment of the implanted source/drain regions, thereby avoiding or mitigating misalignment problems experienced in conventional methods and facilitating scaling of memory cell dimensions.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.